三维异构嵌入式系统集成平台MorPACK的热分析研究

Jin-Ju Chue, Chih-Chyau Yang, Shih-Lun Chen, Chun-Chieh Chiu, Yi-Jun Liu, Chun-Chieh Chu, Chien‐Ming Wu, Chun-Ming Huang
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引用次数: 1

摘要

本文给出了三维异构嵌入式系统集成MorPACK (morphing package)平台的热分析结果。MorPACK平台由由裸模、基板、连接桥和焊球组成的异构子模块堆叠而成。由于MorPACK平台具有微小、非均质和可积的特点,因此需要采用高密度层流结构制造。强制对流的冷却能力受到限制。本研究提出了该三维结构的一个重要特征,以及优化MorPACK结构热解决方案的两个指示。该特性表明,最低层具有最佳的冷却条件,因此应将功耗最高的裸模芯片放置在最低层。它可以使消耗0.45瓦的芯片比放在顶层的芯片冷却12度。其中一个迹象表明,垂直导热系数可以通过填充整个MorPACK与模具材料提高。这一技能有效地冷却了0.45 w消耗芯片比非填充结构多10度。另一个指示显示移除连接桥并切断基板以使芯片放置的房间空间。结果表明,MorPACK的高度和体积可降低50%,并可减小外平面的热阻。
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A study on thermal analysis for 3D heterogenous embedded system integration platform MorPACK
This paper presents a thermal analysis result for a 3D heterogeneous embedded system integration MorPACK (morphing package) platform. The MorPACK platform is stacked by heterogeneous submodules composed of bare dies, a substrate, connection bridges, and solder balls. Since the tiny, heterogeneous and integrable characteristics of MorPACK platform, it needs to be fabricated in high-density and laminar structure. The cooling ability of forced convection is restricted. This study presents an important characteristic for this 3D structure and two indications to optimize thermal solution for MorPACK structure. The characteristic shows the lowest layer owns the best cooling condition, so the bare die chip with highest power consumption should be placed on the lowest layer. It achieves cooling a 0.45-W consuming chip by 12-degree more than it put on the top layer. One of the indications shows the vertical thermal conductivity can be improved by filling up whole MorPACK with mold material. This skill efficiently cools down the 0.45-W consuming chip by 10-degree more than non-filled-up structure. The other indication shows removing the connection bridges and cutting out the substrate to make a room space for chip placement. With result shown, 50 % height and volume of MorPACK can be minimized and also reduce thermal resistance in out-plan direction.
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