SC1:先进CMOS技术下的电路设计:如何设计更低的电源电压

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Pub Date : 2015-03-19 DOI:10.1109/ISSCC.2015.7063154

W. Dehaene

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引用次数: 1

摘要

技术规模化降低了供电电压。对于40nm及以上的先进CMOS技术节点，这带来了具体的挑战。特别是，模拟电路需要专门的设计方法和创新技术。保持高精度，减少可用信号摆动，同时保持能量消耗在合理的范围内，是许多电路设计人员面临的挑战。技术变化和泄漏的增加只会使情况变得更糟。

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SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages

Technology scaling brings lower supply voltages. For advanced CMOS technology nodes of 40nm and beyond, this leads to specific challenges. In particular, analog circuits require specialized design approaches and innovative techniques. Maintaining high precision with reduced available signal swing while keeping energy consumption within reasonable bounds has presented challenges for many circuit designers. Increased technological variability and leakage only make this worse.

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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