Novel mesa isolation using CMP for planarization of 0.35/0.25 um SOI

CMP has been applied to SOI mesa isolation, with good results. Electrical leakage is comparable to that seen on mesa sidewall isolated structures, and there is no indication of contamination or mechanical damage to the transistors. In addition to the individual transistor data, we measured fully operational inverter chains having 640 stages. The yield of these inverter chains is comparable to that of sidewall isolated structures. This is further indication of the viability of the CMP planarization process at isolation. Further work is needed to optimize CMP conditions for isolation, but all indications to date are that it is a viable process for planarization.