A. Keshavarz, Gregory S. Spawn, Nelson Delos Reyes, Rogelio Mincitar, Laurent F. Dion
{"title":"非易失性存储器可靠性测试的复杂性是由测试结构引起的","authors":"A. Keshavarz, Gregory S. Spawn, Nelson Delos Reyes, Rogelio Mincitar, Laurent F. Dion","doi":"10.1109/IIRW.2010.5706515","DOIUrl":null,"url":null,"abstract":"This paper shows the sensitivity of the non-volatile memory reliability test to the test structure design and the pad sharing with other devices. Detailed results are presented to show how other devices on the same test structure can interfere with the EEPROM endurance test results and cause dramatic shifts in the data.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"2274 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Complexities of the non-volatile memory reliability testing caused by the test structure\",\"authors\":\"A. Keshavarz, Gregory S. Spawn, Nelson Delos Reyes, Rogelio Mincitar, Laurent F. Dion\",\"doi\":\"10.1109/IIRW.2010.5706515\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper shows the sensitivity of the non-volatile memory reliability test to the test structure design and the pad sharing with other devices. Detailed results are presented to show how other devices on the same test structure can interfere with the EEPROM endurance test results and cause dramatic shifts in the data.\",\"PeriodicalId\":332664,\"journal\":{\"name\":\"2010 IEEE International Integrated Reliability Workshop Final Report\",\"volume\":\"2274 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Integrated Reliability Workshop Final Report\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2010.5706515\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Integrated Reliability Workshop Final Report","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2010.5706515","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Complexities of the non-volatile memory reliability testing caused by the test structure
This paper shows the sensitivity of the non-volatile memory reliability test to the test structure design and the pad sharing with other devices. Detailed results are presented to show how other devices on the same test structure can interfere with the EEPROM endurance test results and cause dramatic shifts in the data.