26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.