Impact of substrate bias on the mobility of n-type ɷ-gate SOI nanowire MOSFETs

This work presents the impact of substrate bias on the mobility of high-$\mathbf \kappa$/metal gate n-type $\Omega$-gate SOI nanowire MOS transistors. The analysis is performed through experimental measurements and tridimensional numerical simulations. Mobility and its degradation coefficients are extracted using the Y-function method. The results showed that back bias increase has a beneficial effect on mobility for negative voltages and up to 10V, due to reduction in surface roughness scattering. But for higher back bias levels, mobility starts undergoing severe degradation. Simulations show that strong positive back bias drags the inversion layer down to the second interface, where mobility is shown to be lower.