瓦级毫米波CMOS功率放大器的大规模功率组合和线性化

R. Bhat, A. Chakrabarti, H. Krishnaswamy
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引用次数: 36

摘要

采用器件堆叠的开关级放大器最近已经被探索,以满足在毫米波频率下在大约20dBm的中等功率水平下的有效功率放大的挑战。在本文中,我们提出使用一种单步、大规模(8路)、75%效率的集总四分之一波功率组合器,该组合器与堆叠类放大器单元共同设计,以实现q波段45nm SOI CMOS放大器,其峰值Psat为27.2dBm (>0.5W),峰值PAE为10.7%,Psat平坦度为1dB,几乎覆盖了整个q波段(3346GHz)。该测量的输出功率水平比先前报道的毫米波硅PAs高约5倍。为了支持具有高平均效率的复杂调制,我们还提出了一种新的线性化架构,该架构结合了大规模功率组合,电源开关和动态负载调制的线性化效率。第二款完全集成的42.5GHz 45nm SOI CMOS PA基于该架构实现,在6dB回退时实现了60%的峰值效率。
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Large-scale power-combining and linearization in watt-class mmWave CMOS power amplifiers
Switching-class PAs employing device-stacking have been recently explored to meet the challenge of efficient power amplification at mmWave frequencies at moderate power levels of around 20dBm. In this paper, we propose the use of a single-step, large-scale (8-way), 75%-efficient lumped quarterwave power combiner that is co-designed with stacked Class-Elike PA unit cells to enable a Q-band 45nm SOI CMOS PA with a peak Psat of 27.2dBm (>0.5W), peak PAE of 10.7% and 1dB flatness in Psat over nearly the entire Q-band (3346GHz). This measured output power level is approximately 5 × higher than prior reported mmWave silicon PAs. In order to support complex modulations with high average-efficiency, we also propose a novel linearizing architecture that combines largescale power combining, supply-switching for efficiency under backoff and dynamic load modulation for linearization. A second fully-integrated 42.5GHz 45nm SOI CMOS PA is implemented based on this architecture and achieves 60% of the peak efficiency at 6dB back-off.
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