M. Hsieh, T. Yew, Y. Huang, Y. C. Wang, W. Wang, Y. Lee, J. H. Lee
{"title":"具有简单BIST的晶圆级测试阵列，可加快电路可靠性的工艺开发","authors":"M. Hsieh, T. Yew, Y. Huang, Y. C. Wang, W. Wang, Y. Lee, J. H. Lee","doi":"10.1109/IIRW.2015.7437072","DOIUrl":null,"url":null,"abstract":"Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Wafer level test arrays with simple BIST to expedite process development for circuit reliability\",\"authors\":\"M. Hsieh, T. Yew, Y. Huang, Y. C. Wang, W. Wang, Y. Lee, J. H. Lee\",\"doi\":\"10.1109/IIRW.2015.7437072\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.\",\"PeriodicalId\":120239,\"journal\":{\"name\":\"2015 IEEE International Integrated Reliability Workshop (IIRW)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Integrated Reliability Workshop (IIRW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2015.7437072\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2015.7437072","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Wafer level test arrays with simple BIST to expedite process development for circuit reliability
Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.
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