混合信号系统故障等价的概率测度

M. Soma
{"title":"混合信号系统故障等价的概率测度","authors":"M. Soma","doi":"10.1109/VTEST.1991.208135","DOIUrl":null,"url":null,"abstract":"A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"375 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Probabilistic measures of fault equivalence in mixed-signal systems\",\"authors\":\"M. Soma\",\"doi\":\"10.1109/VTEST.1991.208135\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.<<ETX>>\",\"PeriodicalId\":157539,\"journal\":{\"name\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"volume\":\"375 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1991.208135\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208135","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

本文对模拟-数字混合电路和系统中的故障等效进行了研究,重点介绍了等效概念的理论分析以及采样-保持、数模转换器和模数转换器三类电路的实验结果。虽然故障等价在数字故障模型中得到了很好的理解,但在模拟故障模型中仍然是一个相当新的概念。这个概念在混合信号故障模型中也是有效的,但是等效性必须在频域中定义,并且在某些情况下,必须从概率的角度来处理。实验结果既包括经典数字故障卡滞模型引起的故障效应,也包括模拟故障如超规范性能、非线性等。对于每一类电路,我们都进行了大量的仿真来研究其故障行为,并进行了实验测量来验证这些行为以及确认等效定义的有效性。本研究的主要应用是测试生成和故障诊断,类似于数字等效故障在等效类测试向量定义中的应用
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Probabilistic measures of fault equivalence in mixed-signal systems
A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.<>
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