亚微米LOCOS隔离特性

1995 IEEE International SOI Conference Proceedings Pub Date : 1995-10-03 DOI:10.1109/SOI.1995.526488

J.W. Thomas, J. E. Chung, C. Keast

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引用次数: 4

摘要

对于未来的VLSI技术，确保可接受的器件隔离变得越来越重要。本研究探讨了亚微米LOCOS分离的基本变量，包括顶层硅厚度、应力消除氧化物(SRO)厚度、场过氧化率和场植入条件。研究了这些变量如何影响最小可实现隔离间距以及MOS侧门控的易感性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Characteristics of submicrometer LOCOS isolation

For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined.

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1995 IEEE International SOI Conference Proceedings

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