{"title":"消音器!基板噪声耦合分析工具","authors":"P. Birrer, T. Fiez, K. Mayaram","doi":"10.1109/SOCC.2004.1362367","DOIUrl":null,"url":null,"abstract":"Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"411 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Silencer!: a tool for substrate noise coupling analysis\",\"authors\":\"P. Birrer, T. Fiez, K. Mayaram\",\"doi\":\"10.1109/SOCC.2004.1362367\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips.\",\"PeriodicalId\":184894,\"journal\":{\"name\":\"IEEE International SOC Conference, 2004. Proceedings.\",\"volume\":\"411 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International SOC Conference, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2004.1362367\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International SOC Conference, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2004.1362367","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Silencer!: a tool for substrate noise coupling analysis
Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips.
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