CMOS技术路线图投影包括寄生效应

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI:10.1109/VTSA.2009.5159299

Lan Wei, F. Boeuf, T. Skotnicki, H. Wong

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引用次数: 15

摘要

在本文中，我们通过考虑寄生电容来重新审视Si CMOS路线图投影，寄生电容会显著影响32nm以上技术的器件性能。对电容元件进行了解析建模，并考察了不同的设计原则。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CMOS technology roadmap projection including parasitic effects

In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.

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2009 International Symposium on VLSI Technology, Systems, and Applications

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