Fractional implantation area effects on patterned ion-cut silicon layer transfer

By masking the gate dielectric area of MOS devices during hydrogen implantation, patterned ion-cut can transfer processed IC device layers to other substrates (Lee et al. 1996; Roberds et al. 1998; Yun et al. 1998). Previous results showed that a 16 /spl mu/m/spl times/16 /spl mu/m nonimplanted region can be cleaved with a 4 /spl mu/m implanted area surrounding it. However, surface morphology of the cleaved Si(100) samples was rough, with a total thickness variation (TTV) of /spl sim/0.4 /spl mu/m for a 1.3 /spl mu/m-thick silicon layer transfer. In order to improve the roughness, we have investigated the fractional implantation area (FIA) effects on the transferred layer surface morphology.