基于lssd的VLSI逻辑电路延迟测试优化技术

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208165

David M. Wu

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引用次数: 1

摘要

本文介绍了一种用于电平敏感扫描(LSSD)电路的优化延迟测试技术。介绍了在六种LSSD测试芯片的四种不同逻辑组中提高延迟测试效率的方法。在产品质量水平方面，对使用总频闪定时和每针频闪定时的两种延迟测试测量进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An optimized delay testing technique for LSSD-based VLSI logic circuits

In this paper, an optimized delay testing technique used in level sensitive scan design (LSSD) circuits is described. Methods of improving delay test effectiveness in four different logic groups of six LSSD test chips are illustrated. Comparison of two delay testing measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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