Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino
{"title":"设计方面的4 Mbit 0.18 /spl mu/m 1T1MTJ切换MRAM存储器","authors":"Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino","doi":"10.1109/ICICDT.2004.1309940","DOIUrl":null,"url":null,"abstract":"A 4 Mbit \"Toggle\" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The \"Toggle\" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"315 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design aspects of a 4 Mbit 0.18 /spl mu/m 1T1MTJ toggle MRAM memory\",\"authors\":\"Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino\",\"doi\":\"10.1109/ICICDT.2004.1309940\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 4 Mbit \\\"Toggle\\\" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The \\\"Toggle\\\" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"315 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309940\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309940","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design aspects of a 4 Mbit 0.18 /spl mu/m 1T1MTJ toggle MRAM memory
A 4 Mbit "Toggle" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The "Toggle" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.