{"title":"并行模式生成器编程","authors":"M. Kanzaki, M. Ishida","doi":"10.1109/TEST.1991.519775","DOIUrl":null,"url":null,"abstract":"This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"PROGRAMMING FOR PARALLEL PATTERN GENERATORS\",\"authors\":\"M. Kanzaki, M. Ishida\",\"doi\":\"10.1109/TEST.1991.519775\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.\",\"PeriodicalId\":272630,\"journal\":{\"name\":\"1991, Proceedings. International Test Conference\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1991, Proceedings. International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1991.519775\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991, Proceedings. International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1991.519775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.
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