Integrate and Fire Neuron Implementation using CMOS Predictive Technology Model for 32nm

The propose of this work is to evolve the studies on neuromorphic circuits by simulating transistors models that look the most with the ones used in commercial process. Since most of data about company models contain a restricted access, some universities provide predictions models to reproduce the real ones. In this paper we present a silicon analog integrate and fire neuron (I&F), proposed by G. Indiveri as a part of a neuromorphic device. Using 32nm CMOS technology simulated in LTspice with BSIM4v4 and applying predictive parameters provides by Predictive Technology Model (PTM), we were able to reduce the source power, to 0.9V, and chip size of the latest design which was implemented using a 180nm CMOS process at 1.8 power supply.