22.3用于28nm FDSOI CMOS自适应153fJ/b光接收器的4至11ghz注入锁定四分之一速率时钟

M. Raj, S. Saeedi, A. Emami-Neyestanak
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引用次数: 22

摘要

现代SoC系统对片上时钟的产生和分布有严格的要求。基于环形振荡器(RO)的注入锁定(IL)时钟过去已被用于提供低功耗、低面积和低抖动的解决方案。基于环的注入锁定振荡器(ILO)也可用于从没有分频的参考时钟产生正交相位,这对于半速率和四分之一速率CDR是理想的。然而,ILO固有的锁定范围小,使其不太适合宽带应用。此外,由于PVT的变化,自由运行频率的漂移可能导致抖动性能差和锁定故障。将锁相环添加到ILO中提供频率跟踪。然而,锁相环辅助技术具有导致抖动峰值的二阶特性。它们还增加了设计复杂性和功耗。我们提出了一种频率跟踪方法,该方法利用正交反相器中IL的动态特性来增加有效锁定范围。该正交锁相环(QLL)用于为4通道光接收机以四分之一速率转发时钟产生精确的时钟相位。QLL在每个信道上驱动一个ILO,没有任何中继器用于本地正交时钟生成。每个地方劳工组织都有相位校准的工作台能力。在28nm FDSOI技术中,接收器通过自适应体偏置(BB)保持宽数据速率(16至32Gb/s)的每比特能量消耗。
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22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS
Modern SoC systems impose stringent requirements on on-chip clock generation and distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the past to provide a low-power, low-area and low-jitter solution. Ring-based injection-locked oscillators (ILO) can also be used to generate quadrature phases from a reference clock without frequency division, which is desirable for half-rate and quarter-rate CDR. However, ILO inherently has a small locking range making it less suitable for wideband applications. In addition, drift in the free-running frequency due to PVT variations may lead to poor jitter performance and locking failures. Adding a PLL to an ILO provides frequency tracking. However, PLL-aided techniques have second-order characteristics that lead to jitter peaking. They also add design complexity and power consumption . We present a frequency-tracking method that exploits the dynamics of IL in a quadrature RO to increase the effective locking range. This quadrature locked loop (QLL) is used to generate accurate clock phases for a 4-channel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains per-bit energy consumption across wide data-rates (16 to 32Gb/s) by adaptive body biasing (BB) in a 28nm FDSOI technology.
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