{"title":"会话T4B:教程:新兴的非易失性存储器:器件、电路和体系结构","authors":"Guanyu Sun","doi":"10.1109/SOCC.2015.7406889","DOIUrl":null,"url":null,"abstract":"In order to mitigate the problem of “memory wall”, various emerging non-volatile memory (NVM) technologies have been proposed to replace traditional ones. These emerging NVMs include STT-RAM, PCRAM, RRAM, RM, etc. Compared to traditional memory technologies, they have advantages of near-zero standby-power, high storage density, and non-volatility, which make them competitive for future memory hierarchy design. However, it is inefficient to directly apply these NVMs in existing memory architectures. On the one hand, these NVMs have their own limitations, such as long write latency, high write energy, limited write numbers, etc. Thus, proper architecture modification is required to adopt them into traditional memory hierarchy. On the other hand, the unique features of these NVMs enable new memory architectures in memory subsystem and also induce new challenges to be solved at the same time. In this tutorial, we first briefly review device level background of these emerging NVMs. Then, we introduce the tool NVMSim for their circuit level modeling. At last, we investigate their implication for memory architecture design.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Session T4B: Tutorial: Emerging non-volatile memory: Device, circuit, and architecture\",\"authors\":\"Guanyu Sun\",\"doi\":\"10.1109/SOCC.2015.7406889\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to mitigate the problem of “memory wall”, various emerging non-volatile memory (NVM) technologies have been proposed to replace traditional ones. These emerging NVMs include STT-RAM, PCRAM, RRAM, RM, etc. Compared to traditional memory technologies, they have advantages of near-zero standby-power, high storage density, and non-volatility, which make them competitive for future memory hierarchy design. However, it is inefficient to directly apply these NVMs in existing memory architectures. On the one hand, these NVMs have their own limitations, such as long write latency, high write energy, limited write numbers, etc. Thus, proper architecture modification is required to adopt them into traditional memory hierarchy. On the other hand, the unique features of these NVMs enable new memory architectures in memory subsystem and also induce new challenges to be solved at the same time. In this tutorial, we first briefly review device level background of these emerging NVMs. Then, we introduce the tool NVMSim for their circuit level modeling. At last, we investigate their implication for memory architecture design.\",\"PeriodicalId\":329464,\"journal\":{\"name\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2015.7406889\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2015.7406889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Session T4B: Tutorial: Emerging non-volatile memory: Device, circuit, and architecture
In order to mitigate the problem of “memory wall”, various emerging non-volatile memory (NVM) technologies have been proposed to replace traditional ones. These emerging NVMs include STT-RAM, PCRAM, RRAM, RM, etc. Compared to traditional memory technologies, they have advantages of near-zero standby-power, high storage density, and non-volatility, which make them competitive for future memory hierarchy design. However, it is inefficient to directly apply these NVMs in existing memory architectures. On the one hand, these NVMs have their own limitations, such as long write latency, high write energy, limited write numbers, etc. Thus, proper architecture modification is required to adopt them into traditional memory hierarchy. On the other hand, the unique features of these NVMs enable new memory architectures in memory subsystem and also induce new challenges to be solved at the same time. In this tutorial, we first briefly review device level background of these emerging NVMs. Then, we introduce the tool NVMSim for their circuit level modeling. At last, we investigate their implication for memory architecture design.