用于32nm以下HP和LSTP应用的la掺杂金属/高k nMOSFET

2009 International Symposium on VLSI Technology, Systems, and Applications Pub Date : 2009-04-27 DOI:10.1109/VTSA.2009.5159290

C. Park, J. Yang, M. Hussain, C. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. Kirsch, B. H. Lee, H. Tseng, R. Jammy

{"title":"用于32nm以下HP和LSTP应用的la掺杂金属/高k nMOSFET","authors":"C. Park, J. Yang, M. Hussain, C. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. Kirsch, B. H. Lee, H. Tseng, R. Jammy","doi":"10.1109/VTSA.2009.5159290","DOIUrl":null,"url":null,"abstract":"This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application\",\"authors\":\"C. Park, J. Yang, M. Hussain, C. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. Kirsch, B. H. Lee, H. Tseng, R. Jammy\",\"doi\":\"10.1109/VTSA.2009.5159290\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159290\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159290","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文介绍了掺la高k/金属栅极堆叠的nmosfet的结果，以了解其在32nm以下LSTP和HP应用中的适用性。32nm栅极长度晶体管具有优异的离子off特性，PBTI结果满足32nm技术节点的要求。此外，本文还首次研究了掺la高k/金属栅堆器件中Vt的变化。结果表明，采用金属电极抑制了Vt变异性，而没有观察到由于高k介电体的la掺杂而引起的额外参数波动。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2009 International Symposium on VLSI Technology, Systems, and Applications

自引率

0.00%

发文量