Utilizing a Novel Universal Quantum Gate in the Design of Fault-Tolerant Architecture

In nano communication, fault-tolerant networks play a crucial role in error control. A significant practical challenge for nanocircuits is their ability to transmit information over networks to different endpoints. Fault-tolerant and reversible circuits have control error problems. The advantage of a quantum gate-based architecture is that it prevents heat loss, and it has been extensively researched. In this article, we have developed reversible multiplexers (mux's), half-adder (HA), and full-adder (FA) and latches that are fault-tolerant by making use of new gate and implementing them on the IBM Qiskit platform. A power-efficient and fault-tolerant mux's and latches is proposed that uses reversible gates to preserve parity. Multiplexer kinds such as 2:1, 4:1, and n:1 is covered in depth by the new Parity Preserving Multiplexer (PPM) gate and verified by IBM-Qiskit. An algorithmic design for an n:1 multiplexer is invented. In order to assess a PPM gate effectiveness, 13 standard Boolean functions and 8 standard types of gates are implemented. The PPM quantum gate is built using quantum assembly code (QAC), which runs on IBM Quantum Lab and IBM Quantum Composer platforms to measure the output qubits. Additional HA, muxes, and latches design led to the code creation in the Qiskit platform, which was used to measure the output qubits. A comparison of the D-latch, T-latch, JK-latch, and mux designs with existing circuits shows a reduction in quantum cost (qc) and junk output (go) and the implementation of a custom design in the IBM-Qiskit platform to measure output qubits is a first time in literature.