Highly Reliable, Stable, and Store Energy Efficient 8T/9T-2D-2MTJ NVSRAMs

Non-Volatile SRAMs exhibit zero static power loss which is eminent for future on-chip memories. Thus, in this brief, two simple and scalable designs of NVSRAM (8T&9T-2D-2MTJ) having key properties (high speed, low dynamic power, stability and reliability) have been investigated. To make the circuit scalable, the perpendicular magneto anisotropy (PMA) based magnetic tunnel junction (MTJ) (works on the spin transfer torque (STT) & spin orbit torque (SOT) interplay phenomenon) are used as an NV cell in the proposed circuit. A small pulse of current is required for store and restore operation of NV cell, which can effectively accommodate through cross coupled inverters, makes external write circuitry redundant and reduce the complexity of bit cell. The 8T/9T-2MTJ circuit provides an approximate 38%/35% decrease in store delay along with 7%/32% power efficiency as compared to existing NVSRAMs. The hold and write stability of 8T-2MTJ cell is better. However, the read stability of 9T-2MTJ cell is better. The physics-based field-free STT-SOT MTJ model and 40 nm UMC CMOS design kit based NVSRAM make the circuit practically viable. The Process variation analysis and monte carlo analysis suggests that the proposed NVSRAMs are reliable for a wide range (−25 °C to 125 °C) of temperatures and supply voltages. The 8*8 array design of proposed NVSRAMs shows promising results for dense memory architecture.