{"title":"SOI 无结 FinFET 中阈值电压和阈下摆动的改进型傅里叶级数分析模型","authors":"Shara Mathew, Sriraj Chennamadhavuni, Rathnamala Rao","doi":"10.1016/j.micrna.2024.207848","DOIUrl":null,"url":null,"abstract":"<div><p>In this work, Fourier series-based analytical models for threshold voltage (V<sub>th</sub>) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of V<sub>th</sub> for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm.</p></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":null,"pages":null},"PeriodicalIF":2.7000,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET\",\"authors\":\"Shara Mathew, Sriraj Chennamadhavuni, Rathnamala Rao\",\"doi\":\"10.1016/j.micrna.2024.207848\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In this work, Fourier series-based analytical models for threshold voltage (V<sub>th</sub>) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of V<sub>th</sub> for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm.</p></div>\",\"PeriodicalId\":100923,\"journal\":{\"name\":\"Micro and Nanostructures\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.7000,\"publicationDate\":\"2024-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Micro and Nanostructures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2773012324000979\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"PHYSICS, CONDENSED MATTER\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012324000979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET
In this work, Fourier series-based analytical models for threshold voltage (Vth) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of Vth for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm.