{"title":"用于消除直流电容的对称和多相交错梯形降压器","authors":"Loai G. Salem","doi":"10.1109/TVLSI.2024.3392617","DOIUrl":null,"url":null,"abstract":"To improve power density, a symmetric switched-capacitor (SC) ladder buck (SLB) is proposed in this brief that eliminates the fixed ladder in an SC ladder buck (SCLB) by tying the dc nodes in two 180°-phase-shifted cells together. Unlike flying capacitor multilevel converters (FCMCs) that minimize the inductor current ripple, the ladder topology within an SCLB splits the inductor current optimally among the ladder switches, such that the overall equivalent output resistance is minimized. M-phase interleaving is proposed in this brief to allow SLB to regain this current splitting capability when operating via duty cycles larger than 0.5. Simulation results of a six-level four-phase design in 180-nm CMOS verify the performance advantages of the proposed topology.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination\",\"authors\":\"Loai G. Salem\",\"doi\":\"10.1109/TVLSI.2024.3392617\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To improve power density, a symmetric switched-capacitor (SC) ladder buck (SLB) is proposed in this brief that eliminates the fixed ladder in an SC ladder buck (SCLB) by tying the dc nodes in two 180°-phase-shifted cells together. Unlike flying capacitor multilevel converters (FCMCs) that minimize the inductor current ripple, the ladder topology within an SCLB splits the inductor current optimally among the ladder switches, such that the overall equivalent output resistance is minimized. M-phase interleaving is proposed in this brief to allow SLB to regain this current splitting capability when operating via duty cycles larger than 0.5. Simulation results of a six-level four-phase design in 180-nm CMOS verify the performance advantages of the proposed topology.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-04-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10510403/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10510403/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination
To improve power density, a symmetric switched-capacitor (SC) ladder buck (SLB) is proposed in this brief that eliminates the fixed ladder in an SC ladder buck (SCLB) by tying the dc nodes in two 180°-phase-shifted cells together. Unlike flying capacitor multilevel converters (FCMCs) that minimize the inductor current ripple, the ladder topology within an SCLB splits the inductor current optimally among the ladder switches, such that the overall equivalent output resistance is minimized. M-phase interleaving is proposed in this brief to allow SLB to regain this current splitting capability when operating via duty cycles larger than 0.5. Simulation results of a six-level four-phase design in 180-nm CMOS verify the performance advantages of the proposed topology.
期刊介绍：
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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