An analytical model of P+ SiC core-shell JLFETs to analyze the performance for higher breakdown voltages applications

In this article, we proposed a core-shell (CS) architecture that uses the silicon carbide (SiC) as a nanowire for higher breakdown voltages in a Junctionless field effect transistor (JLFET). The P⁺ core-shell improves the electrostatic integrity and reduces lateral band-to-band tunneling in SiC JLFET. Furthermore, the SiC is wide band gap material which helps to achieve the full volume depletion in JLFET at such short channel lengths. Thus, the OFF-state current in P⁺ SiC CS JLFET has reduced to 10⁻¹⁶ μA even at temperature 600 K and V_DS = 2.0 V. The P⁺ SiC CS JLFET shows significant performance even at higher drain voltages. Hence, we investigate the P⁺ SiC CS JLFET for higher breakdown voltages with the impact of higher temperatures. In addition, the impact of higher drain voltages with higher temperatures is also examined. This paper presents an analytical model for P⁺ SiC CS JLFETs which considers Poisson's equation for nanowires as well as the surface potential at the threshold voltage (V_th) and electric field at the zero point (E_z). The model shows that the surface potential and the electric fields in nanowires are essential for an accurate estimation of the drain current. In addition to the numerical modeling results provided by SILVACO TCAD, the performance of the proposed analytical model was compared with simulation results. The results showed good agreement between the simulations and the proposed compact model. This indicates that the proposed model can be used to provide accurate drain current predictions in nanoscale transistors.