Electron and spin transport in semiconductor and magnetoresistive devices

As the scaling of CMOS-based technology shows signs of an imminent saturation, employing the second intrinsic electron characteristics – the electron spin – is attractive to further boost the performance of integrated circuits and to introduce new computational paradigms. The spin promises to offer an additional functionality to charge-based CMOS circuitry. Spin injection and spin manipulation by gate-induced electrics field at room temperatures were successfully demonstrated in semiconductor channels, expectations that such spin-driven devices appear in digital circuits to complement or even replace CMOS become credible.

On the memory side, the nonvolatile CMOS-compatible spin-transfer torque (STT) and the spin–orbit torque magnetoresistive random access memories (MRAMs) are already competing with flash memory and even SRAM for embedded applications.

To accurately model spin and charge transport and torques in magnetic tunnel junctions, we innovatively extend the spin and charge transport equations to multi-layered structures consisting of normal and ferromagnetic metal layers separated by tunnel barriers. We validate our approach by modeling the magnetization dynamics in ultra-scaled MRAM cells. A multi-bit operation is predicted in an MRAM cell with a composite free layer.