{"title":"带有叠层 SiO2/HfO2 亚门电介质的硅场效应锥形 GAA 纳米晶体管仿真","authors":"N. V. Masal’skii","doi":"10.1134/s1063739724600274","DOIUrl":null,"url":null,"abstract":"<h3 data-test=\"abstract-sub-heading\">Abstract</h3><p>The issues of modeling the electrical characteristics of a silicon conical field-effect gate-all-around (GAA) nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully encompassing conical gate with a stacked subgate SiO<sub>2</sub>/HfO<sub>2</sub> oxide, taking into account the influence of the charge of the interfacial trap at the Si/SiO<sub>2</sub> interface, is developed. To model the potential distribution in a conical working area under the condition of a constant trap density, an analytical solution of the Poisson equation is obtained using the parabolic approximation method in the cylindrical coordinate system with the corresponding boundary conditions. The potential model is used to develop an expression for the drain current of a GAA nanotransistor with a stacked subgate oxide. The key electrical and physical characteristics are numerically studied depending on the density of the traps and the thickness of the SiO<sub>2</sub> and HfO<sub>2</sub> layers.</p>","PeriodicalId":21534,"journal":{"name":"Russian Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Simulation of Silicon Field-Effect Conical GAA Nanotransistors with a Stacked SiO2/HfO2 Subgate Dielectric\",\"authors\":\"N. V. Masal’skii\",\"doi\":\"10.1134/s1063739724600274\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<h3 data-test=\\\"abstract-sub-heading\\\">Abstract</h3><p>The issues of modeling the electrical characteristics of a silicon conical field-effect gate-all-around (GAA) nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully encompassing conical gate with a stacked subgate SiO<sub>2</sub>/HfO<sub>2</sub> oxide, taking into account the influence of the charge of the interfacial trap at the Si/SiO<sub>2</sub> interface, is developed. To model the potential distribution in a conical working area under the condition of a constant trap density, an analytical solution of the Poisson equation is obtained using the parabolic approximation method in the cylindrical coordinate system with the corresponding boundary conditions. The potential model is used to develop an expression for the drain current of a GAA nanotransistor with a stacked subgate oxide. The key electrical and physical characteristics are numerically studied depending on the density of the traps and the thickness of the SiO<sub>2</sub> and HfO<sub>2</sub> layers.</p>\",\"PeriodicalId\":21534,\"journal\":{\"name\":\"Russian Microelectronics\",\"volume\":\"17 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-07-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Russian Microelectronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1134/s1063739724600274\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Russian Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1134/s1063739724600274","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
Simulation of Silicon Field-Effect Conical GAA Nanotransistors with a Stacked SiO2/HfO2 Subgate Dielectric
Abstract
The issues of modeling the electrical characteristics of a silicon conical field-effect gate-all-around (GAA) nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully encompassing conical gate with a stacked subgate SiO2/HfO2 oxide, taking into account the influence of the charge of the interfacial trap at the Si/SiO2 interface, is developed. To model the potential distribution in a conical working area under the condition of a constant trap density, an analytical solution of the Poisson equation is obtained using the parabolic approximation method in the cylindrical coordinate system with the corresponding boundary conditions. The potential model is used to develop an expression for the drain current of a GAA nanotransistor with a stacked subgate oxide. The key electrical and physical characteristics are numerically studied depending on the density of the traps and the thickness of the SiO2 and HfO2 layers.
期刊介绍：
Russian Microelectronics covers physical, technological, and some VLSI and ULSI circuit-technical aspects of microelectronics and nanoelectronics; it informs the reader of new trends in submicron optical, x-ray, electron, and ion-beam lithography technology; dry processing techniques, etching, doping; and deposition and planarization technology. Significant space is devoted to problems arising in the application of proton, electron, and ion beams, plasma, etc. Consideration is given to new equipment, including cluster tools and control in situ and submicron CMOS, bipolar, and BICMOS technologies. The journal publishes papers addressing problems of molecular beam epitaxy and related processes; heterojunction devices and integrated circuits; the technology and devices of nanoelectronics; and the fabrication of nanometer scale devices, including new device structures, quantum-effect devices, and superconducting devices. The reader will find papers containing news of the diagnostics of surfaces and microelectronic structures, the modeling of technological processes and devices in micro- and nanoelectronics, including nanotransistors, and solid state qubits.
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