Ni Wang, Yu Liang, Wei Zhang, Tingting Wu, Dongning Hao
{"title":"针对 14 位 1-MS/s SAR ADC 的多级抖动前景校准技术","authors":"Ni Wang, Yu Liang, Wei Zhang, Tingting Wu, Dongning Hao","doi":"10.1016/j.mejo.2024.106351","DOIUrl":null,"url":null,"abstract":"<div><p>A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC\",\"authors\":\"Ni Wang, Yu Liang, Wei Zhang, Tingting Wu, Dongning Hao\",\"doi\":\"10.1016/j.mejo.2024.106351\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).</p></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-07-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124000559\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000559","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
摘要
本文提出了一种前景校准方法，以获得 14 位 1-MS/s 逐次逼近寄存器（SAR）模数转换器（CDAC）的分电容数模转换器（CDAC）中的实际权重。由于高分辨率 SAR ADC 的非线性主要是由电容器的不匹配造成的，因此当 SAR ADC 的分辨率超过 12 位时，有必要校准更重要位的权重。通过在校准方案的校准和转换阶段注入多级抖动信号，可以显著提高 SAR ADC 的精度和非线性度。仿真结果表明，在 14 位 split-CDAC SAR ADC 中采用所提出的校准技术后，峰值信噪比（SNDR）和无杂散动态范围（SFDR）分别达到 79.93 dB 和 91.21 dB。此外，积分非线性度 (INL) 达到 0.22 最小有效位 (LSB)。
A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC
A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).
期刊介绍：
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
