基于超轻时间周期 CNN 模型的人工智能加速器,用于心律失常分类。

Shuenn-Yuh Lee, Ming-Yueh Ku, Wei-Cheng Tseng, Ju-Yi Chen
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引用次数: 0

摘要

这项研究提出了一种心律失常分类系统,旨在提高心脏病专家诊断过程的效率。提出的算法包括一个适用于各种心电图数据库的心电图(ECG)数据天真预处理程序。此外,这项研究还提出了一种基于卷积神经网络的超轻量级心律失常分类模型,并结合 R 峰间期特征来表示长期节律信息,从而提高了模型的分类性能。根据美国医学仪器促进协会(AAMI)的分类标准,使用 MIT-BIH 和 NCKU-CBIC 数据库对提出的模型进行了训练和测试,取得了 98.32% 和 97.1% 的高准确率。这项工作将心律失常分类算法应用于基于网络的系统,从而提供了一个图形界面。基于云计算的人工智能(AI)自动分类执行可让心脏病专家和患者即时查看心电图波形情况,从而显著提高医疗检查质量。这项工作还为人工智能加速器的硬件实施设计了定制集成电路。该加速器利用并行化处理元件阵列架构来执行卷积和全连接层操作。它引入了拟议的混合静态技术,将输入和权重静态模式相结合,大幅提高了数据重用率,减少了硬件执行周期和功耗,最终实现了高性能计算。该加速器采用台积电 180 纳米 CMOS 工艺,以芯片形式实现。它的功耗为 122 μW,分类延迟为 6.8 ms,能效为 0.83 μJ/分类。
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AI Accelerator with Ultralightweight Time-Period CNN-Based Model for Arrhythmia Classification.

This work proposes a classification system for arrhythmias, aiming to enhance the efficiency of the diagnostic process for cardiologists. The proposed algorithm includes a naive preprocessing procedure for electrocardiography (ECG) data applicable to various ECG databases. Additionally, this work proposes an ultralightweight model for arrhythmia classification based on a convolutional neural network and incorporating R-peak interval features to represent long-term rhythm information, thereby improving the model's classification performance. The proposed model is trained and tested by using the MIT-BIH and NCKU-CBIC databases in accordance with the classification standards of the Association for the Advancement of Medical Instrumentation (AAMI), achieving high accuracies of 98.32% and 97.1%. This work applies the arrhythmia classification algorithm to a web-based system, thus providing a graphical interface. The cloud-based execution of automated artificial intelligence (AI) classification allows cardiologists and patients to view ECG wave conditions instantly, thereby remarkably enhancing the quality of medical examination. This work also designs a customized integrated circuit for the hardware implementation of an AI accelerator. The accelerator utilizes a parallelized processing element array architecture to perform convolution and fully connected layer operations. It introduces proposed hybrid stationary techniques, combining input and weight stationary modes to increase data reuse drastically and reduce hardware execution cycles and power consumption, ultimately achieving high-performance computing. This accelerator is implemented in the form of a chip by using the TSMC 180 nm CMOS process. It exhibits a power consumption of 122 μW, a classification latency of 6.8 ms, and an energy efficiency of 0.83 μJ/classification.

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