A Hardware and Software Co-Design for Energy-Efficient Neural Network Accelerator With Multiplication-Less Folded-Accumulative PE for Radar-Based Hand Gesture Recognition

This work presents a novel lightweight neural network (NN) model and a dedicated NN accelerator for radar-based hand gesture recognition (HGR). The NN model employs symmetric weights, group 1-D-convolution, and power-of-two (POT) quantization, achieving 92.84% accuracy on a public dataset with only 4.8 k parameters, while reducing parameter storage by 40%. The custom accelerator features a multiplication-less folded-accumulative processing element (PE), group-wise computation optimization, and an efficient scheduling mechanism for fully connected (FC) layers. Implemented on a Xilinx field-programmable gate array (FPGA) board XC7S15 and 65-nm CMOS technology, it surpasses existing solutions in power efficiency and cost-effectiveness, addressing the computational demands for IoT deployment.