A common-mode insensitive thyristor-based latch regenerative comparator for low supply voltage applications

Presented in this article is a new two-stage rail-to-rail regenerative comparator circuit designed for low supply voltage applications. This work introduces a thyristor-based latch for the first time, allowing the comparator to operate from rail-to-rail inputs. The proposed comparator has been post-layout simulated using a standard 65 nm CMOS technology. The worst-case simulation results demonstrate that the comparator exhibits a delay of less than 22ns and consumes only 132 nW of power at a supply voltage of 0.6V and a sample rate of 1 MHz across its full common-mode range. Furthermore, the total input-referred offset voltage (3std + mean) remains below 21 mV throughout the entire rail-to-rail common-mode voltage range. Compared to the conventional single-stage comparator, the proposed circuit showcases an improvement of over 87 % in terms of delay and energy efficiency. Given its dignified performance metrics, this comparator is well-suited for use in low supply voltage applications such as biomedical implants, successive approximation registers analog-to-digital converters (SAR ADCs), Internet of Things (IoT).