A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS

With a 65-nm CMOS process, a V-band wideband injection locking (IL) frequency tripler is proposed by cascading a multiplier and a driver amplifier stage. Concerning high output power and efficiency performance over a wideband locking range (LR), two transformer-based IL topologies are analyzed in the multiplier and driver stages, in which the cross-coupled pair is connected at the input and output ports of the transformer, respectively. Moreover, the active device is carefully designed in terms of the operating point of the harmonic generator and device sizing in the driver amplifier stage. With measurements, the proposed tripler achieves a maximum measured output power of 7.3 dBm with 22.4% output-to-DC power efficiency and 26.8% LR from 50.4 to 66 GHz. Including the output driver amplifier, the IL tripler consumes 24 mW DC power. The measured fundamental and 2nd-harmonic rejection ratios (HRR) are both better than 30 dBc, while the measured phase noise (PN) degradation is in close agreement with the theoretical value.