{"title":"探索 3 纳米节点之后先进背面功率传输网络的热效应","authors":"Haoyu Zhang , Linlin Cai , Haifeng Chen , Binyu Yin , Wangyong Chen","doi":"10.1016/j.mejo.2024.106440","DOIUrl":null,"url":null,"abstract":"<div><div>Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Exploring thermal effects of advanced backside power delivery network beyond 3 nm node\",\"authors\":\"Haoyu Zhang , Linlin Cai , Haifeng Chen , Binyu Yin , Wangyong Chen\",\"doi\":\"10.1016/j.mejo.2024.106440\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-10-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124001449\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001449","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Exploring thermal effects of advanced backside power delivery network beyond 3 nm node
Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.