Qiang Zhao , Jitao Xu , Chunhui Fan , Ziming Wang , Ruitong Hu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu
{"title":"基于闪存/SS 架构的 11 位两步列共享 ADC，适用于 CMOS 图像传感器","authors":"Qiang Zhao , Jitao Xu , Chunhui Fan , Ziming Wang , Ruitong Hu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu","doi":"10.1016/j.mejo.2024.106444","DOIUrl":null,"url":null,"abstract":"<div><div>Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of CMOS image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 × 256 pixel resolution, the simulation results show that the row time of ADC is <span><math><mrow><mn>5</mn><mo>.</mo><mn>4</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span>, the column-level average power consumption is 129.5 <span><math><mi>μ</mi></math></span>W, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor\",\"authors\":\"Qiang Zhao , Jitao Xu , Chunhui Fan , Ziming Wang , Ruitong Hu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu\",\"doi\":\"10.1016/j.mejo.2024.106444\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of CMOS image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 × 256 pixel resolution, the simulation results show that the row time of ADC is <span><math><mrow><mn>5</mn><mo>.</mo><mn>4</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span>, the column-level average power consumption is 129.5 <span><math><mi>μ</mi></math></span>W, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124001486\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001486","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor
Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of CMOS image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 × 256 pixel resolution, the simulation results show that the row time of ADC is , the column-level average power consumption is 129.5 W, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure.
期刊介绍：
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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