有效的肖特基势垒高度调制使用介电偶极为源/漏比接触电阻率的改善

K. Ang, K. Majumdar, K. Matthews, C. Young, C. Kenney, C. Hobbs, P. Kirsch, R. Jammy, R. Clark, S. Consiglio, K. Tapily, Y. Trickett, G. Nakamura, C. Wajda, G. Leusink, M. Rodgers, S. Gausepohl
{"title":"有效的肖特基势垒高度调制使用介电偶极为源/漏比接触电阻率的改善","authors":"K. Ang, K. Majumdar, K. Matthews, C. Young, C. Kenney, C. Hobbs, P. Kirsch, R. Jammy, R. Clark, S. Consiglio, K. Tapily, Y. Trickett, G. Nakamura, C. Wajda, G. Leusink, M. Rodgers, S. Gausepohl","doi":"10.1109/IEDM.2012.6479068","DOIUrl":null,"url":null,"abstract":"We demonstrate statistically significant data for specific contact resistivity (ρ<sub>c</sub>) of sub-10<sup>-8</sup>Ω-cm<sup>2</sup> and sub-2×10<sup>-8</sup>Ω-cm<sup>2</sup> for N-type and P-type Si respectively on 300mm wafer by introducing ultra-thin ALD high-k dielectric layer(s) between the metal and Si. A 6-terminal Cross-Bridge Kelvin (6T-CBK) structure was used for the extraction to achieve excellent resolution in this small ρ<sub>c</sub> range. With the help of measurements from multiple dielectric stacks and Non-Equilibrium Green's Function (NEGF) based quantum transport calculations, we clearly show that the suppression of evanescent metal induced gap states (MIGS) and formation of interface dipole play significant role to reduce the ρ<sub>c</sub> as long as the tunneling resistance of the dielectric stack is small. Finally, transient response, break down mechanism and technology benchmarking are discussed which show promise for sub-14nm node applications.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement\",\"authors\":\"K. Ang, K. Majumdar, K. Matthews, C. Young, C. Kenney, C. Hobbs, P. Kirsch, R. Jammy, R. Clark, S. Consiglio, K. Tapily, Y. Trickett, G. Nakamura, C. Wajda, G. Leusink, M. Rodgers, S. Gausepohl\",\"doi\":\"10.1109/IEDM.2012.6479068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate statistically significant data for specific contact resistivity (ρ<sub>c</sub>) of sub-10<sup>-8</sup>Ω-cm<sup>2</sup> and sub-2×10<sup>-8</sup>Ω-cm<sup>2</sup> for N-type and P-type Si respectively on 300mm wafer by introducing ultra-thin ALD high-k dielectric layer(s) between the metal and Si. A 6-terminal Cross-Bridge Kelvin (6T-CBK) structure was used for the extraction to achieve excellent resolution in this small ρ<sub>c</sub> range. With the help of measurements from multiple dielectric stacks and Non-Equilibrium Green's Function (NEGF) based quantum transport calculations, we clearly show that the suppression of evanescent metal induced gap states (MIGS) and formation of interface dipole play significant role to reduce the ρ<sub>c</sub> as long as the tunneling resistance of the dielectric stack is small. Finally, transient response, break down mechanism and technology benchmarking are discussed which show promise for sub-14nm node applications.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6479068\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6479068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15

摘要

通过在金属和硅之间引入超薄ALD高k介电层,我们得到了在300mm晶圆上n型和p型硅的比接触电阻率(ρc)分别为sub-10-8Ω-cm2和sub-2×10-8Ω-cm2的统计显著数据。采用6端跨桥开尔文(6T-CBK)结构进行提取,在这个小的ρc范围内获得了很好的分辨率。通过对多个介电层的测量和基于非平衡格林函数(Non-Equilibrium Green’s Function, NEGF)的量子输运计算,我们清楚地表明,只要介电层的隧穿阻力较小,抑制倏逝金属诱导隙态(MIGS)和界面偶极子的形成对降低ρc起着重要作用。最后,讨论了该器件的瞬态响应、击穿机制和技术基准测试等方面的研究成果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement
We demonstrate statistically significant data for specific contact resistivity (ρc) of sub-10-8Ω-cm2 and sub-2×10-8Ω-cm2 for N-type and P-type Si respectively on 300mm wafer by introducing ultra-thin ALD high-k dielectric layer(s) between the metal and Si. A 6-terminal Cross-Bridge Kelvin (6T-CBK) structure was used for the extraction to achieve excellent resolution in this small ρc range. With the help of measurements from multiple dielectric stacks and Non-Equilibrium Green's Function (NEGF) based quantum transport calculations, we clearly show that the suppression of evanescent metal induced gap states (MIGS) and formation of interface dipole play significant role to reduce the ρc as long as the tunneling resistance of the dielectric stack is small. Finally, transient response, break down mechanism and technology benchmarking are discussed which show promise for sub-14nm node applications.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
On the degradation of field-plate assisted RESURF power devices Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices MOSFET performance and scalability enhancement by insertion of oxygen layers
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1