W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang
{"title":"真正的7nm平台技术，具有最小的FinFET和最小的SRAM单元，EUV，特殊结构和第三代单扩散中断","authors":"W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang","doi":"10.1109/VLSIT.2018.8510682","DOIUrl":null,"url":null,"abstract":"7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um2 is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"61 2 1","pages":"59-60"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break\",\"authors\":\"W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang\",\"doi\":\"10.1109/VLSIT.2018.8510682\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um2 is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"61 2 1\",\"pages\":\"59-60\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510682\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510682","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break
7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um2 is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.
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