Hardware primitives for packet flow processing architectures

As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements. As Field-programmable gate array (FPGA) technology continues to evolve, its use for packet processing tasks in network devices is expected to grow. Meanwhile, per-flow processing techniques that scale better than per-packet ones are becoming more widespread in network design. Packet flow processing aims at grouping packets that require similar processing tasks in order to perform them efficiently. This paper proposes the definition of hardware primitives that can be assembled and reused to build packet flow processing architectures. These primitives are described and discussed as well as their interconnection strategy. To illustrate the concept, a case study of an implementation of a packet switch architecture is finally presented.