10nm及以上STT-MRAM的低RA磁隧道结阵列与低开关电流和高击穿电压相结合

C. Park, H. Lee, C. Ching, J. Ahn, R. Wang, M. Pakala, S. H. Kang
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引用次数: 14

摘要

STT-MRAM的深度缩放节点(例如低于10 nm的CMOS)需要低电阻面积积(RA)磁隧道结(MTJs)来包含开关电压(Vc)并确保高耐用性。与各种报告相反,我们展示了低ra mtj的系统工程,而不需要交易关键设备属性,并且值得注意的是,具有更高的屏障可靠性。MTJs集成了超薄合成反铁磁层(tSAF)和Co/Pt伪合金钉住层。通过将RA从10降低到5 Ωµm2,显著降低了Vc并实现了5 ns的可靠开关。此外,击穿电压(VBD)也得到了提高。结果表明,MTJ的可调性可扩展到10 nm以下的CMOS,以实现高性能和高可靠性的MRAM。
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Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond
The scaling of STT-MRAM for deeply scaled nodes (e.g. sub-10 nm CMOS) requires low resistance-area-product (RA) magnetic tunnel junctions (MTJs) to contain switching voltage (Vc) and to assure high endurance. In contrast to various reports, we demonstrate systematic engineering of low-RA MTJs without trading off key device attributes and remarkably, with higher barrier reliability. The MTJs integrate an ultra-thin synthetic antiferromagnetic layer (tSAF) with a Co/Pt pseudo-alloy pinned layer. By reducing RA from 10 to 5 Ωµm2, significantly reduced Vc and reliable switching at 5 ns have been achieved. Furthermore, the breakdown voltage (VBD) has been improved. The results suggest that the tunability of MTJ is extended to sub-10 nm CMOS for high-performance and high-reliability MRAM.
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