D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong
{"title":"在200 mm GeSnOI衬底上实现了小于10 nm翅片宽度的GeSn p- finfet:最低SS为63 mV/decade,最高Gm,int为900µS/µm,高场eff为275 cm2/V•S","authors":"D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong","doi":"10.1109/VLSIT.2018.8510693","DOIUrl":null,"url":null,"abstract":"We report the first GeSn p-FinFETs with sub-10 nm fin width (W<inf>Fin</inf>) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (L<inf>CH</inf>) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high G<inf>m,int</inf> of 900 μS/µm (V<inf>DS</inf> of -0.5 V) and G<inf>m,int</inf>/S<inf>sat</inf> of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µ<inf>eff</inf> of 275 cm<sup>2</sup>/V•s (at inversion carrier density N<inf>inv</inf> of 8×10<sup>12</sup> cm<sup>-2</sup>) was also obtained.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"46 1","pages":"197-198"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•s\",\"authors\":\"D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong\",\"doi\":\"10.1109/VLSIT.2018.8510693\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report the first GeSn p-FinFETs with sub-10 nm fin width (W<inf>Fin</inf>) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (L<inf>CH</inf>) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high G<inf>m,int</inf> of 900 μS/µm (V<inf>DS</inf> of -0.5 V) and G<inf>m,int</inf>/S<inf>sat</inf> of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µ<inf>eff</inf> of 275 cm<sup>2</sup>/V•s (at inversion carrier density N<inf>inv</inf> of 8×10<sup>12</sup> cm<sup>-2</sup>) was also obtained.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"46 1\",\"pages\":\"197-198\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510693\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•s
We report the first GeSn p-FinFETs with sub-10 nm fin width (WFin) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (LCH) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high Gm,int of 900 μS/µm (VDS of -0.5 V) and Gm,int/Ssat of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µeff of 275 cm2/V•s (at inversion carrier density Ninv of 8×1012 cm-2) was also obtained.