Seong Jun Yoon, Kwanyong Pak, Hyun Jun Ahn, A. Yoon, S. Im, Byung Jin Cho
{"title":"循环引发化学气相沉积工艺制备超低k高孔隙介质的选择性封孔研究","authors":"Seong Jun Yoon, Kwanyong Pak, Hyun Jun Ahn, A. Yoon, S. Im, Byung Jin Cho","doi":"10.1109/VLSIT.2018.8510630","DOIUrl":null,"url":null,"abstract":"A selective pore-sealing of highly porous ultralow-k (pULK) dielectrics by a cyclic initiated CVD (iCVD) process has been successfully developed. A negligible increase of the pULK thickness and the k value was achieved even after the hermetic pore-sealing. The pore-sealed pULK films show low leakage current and excellent dielectric reliability, comparable to the commercialized low-k dielectric. The selective pore-sealing process does not deposit the pore-sealing layer on Cu surface. The porosity difference between pULK and Cu surfaces is attributed to the origin of the selectivity in the cyclic iCVD process.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"73-74"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Selective Pore-Sealing of Highly Porous Ultralow-k dielectrics for ULSI Interconnects by Cyclic Initiated Chemical Vapor Deposition Process\",\"authors\":\"Seong Jun Yoon, Kwanyong Pak, Hyun Jun Ahn, A. Yoon, S. Im, Byung Jin Cho\",\"doi\":\"10.1109/VLSIT.2018.8510630\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A selective pore-sealing of highly porous ultralow-k (pULK) dielectrics by a cyclic initiated CVD (iCVD) process has been successfully developed. A negligible increase of the pULK thickness and the k value was achieved even after the hermetic pore-sealing. The pore-sealed pULK films show low leakage current and excellent dielectric reliability, comparable to the commercialized low-k dielectric. The selective pore-sealing process does not deposit the pore-sealing layer on Cu surface. The porosity difference between pULK and Cu surfaces is attributed to the origin of the selectivity in the cyclic iCVD process.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"16 1\",\"pages\":\"73-74\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510630\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510630","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Selective Pore-Sealing of Highly Porous Ultralow-k dielectrics for ULSI Interconnects by Cyclic Initiated Chemical Vapor Deposition Process
A selective pore-sealing of highly porous ultralow-k (pULK) dielectrics by a cyclic initiated CVD (iCVD) process has been successfully developed. A negligible increase of the pULK thickness and the k value was achieved even after the hermetic pore-sealing. The pore-sealed pULK films show low leakage current and excellent dielectric reliability, comparable to the commercialized low-k dielectric. The selective pore-sealing process does not deposit the pore-sealing layer on Cu surface. The porosity difference between pULK and Cu surfaces is attributed to the origin of the selectivity in the cyclic iCVD process.