K. Abe, H. Noguchi, E. Kitagawa, N. Shimomura, J. Ito, S. Fujita
{"title":"新型混合DRAM/MRAM设计，降低高性能移动CPU功耗","authors":"K. Abe, H. Noguchi, E. Kitagawa, N. Shimomura, J. Ito, S. Fujita","doi":"10.1109/IEDM.2012.6479019","DOIUrl":null,"url":null,"abstract":"This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"7 1","pages":"10.5.1-10.5.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":"{\"title\":\"Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU\",\"authors\":\"K. Abe, H. Noguchi, E. Kitagawa, N. Shimomura, J. Ito, S. Fujita\",\"doi\":\"10.1109/IEDM.2012.6479019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":\"7 1\",\"pages\":\"10.5.1-10.5.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"31\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6479019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6479019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU
This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).
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