{"title":"基于IP-XACT的异构体系结构的可扩展代码生成框架","authors":"Thomas P. Perry, R. Walke, K. Benkrid","doi":"10.1109/SPL.2011.5782629","DOIUrl":null,"url":null,"abstract":"In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and extensible flow based around the IP-XACT standard, which is gaining support in industry, and link this to a front-end built on the semantics of dataflow process networks and a template-based code generation back-end.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"4 1","pages":"81-86"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"An extensible code generation framework for heterogeneous architectures based on IP-XACT\",\"authors\":\"Thomas P. Perry, R. Walke, K. Benkrid\",\"doi\":\"10.1109/SPL.2011.5782629\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and extensible flow based around the IP-XACT standard, which is gaining support in industry, and link this to a front-end built on the semantics of dataflow process networks and a template-based code generation back-end.\",\"PeriodicalId\":6329,\"journal\":{\"name\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"volume\":\"4 1\",\"pages\":\"81-86\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2011.5782629\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782629","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An extensible code generation framework for heterogeneous architectures based on IP-XACT
In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and extensible flow based around the IP-XACT standard, which is gaining support in industry, and link this to a front-end built on the semantics of dataflow process networks and a template-based code generation back-end.