基于Matlab/Simulink的电力电子控制FPGA快速设计实例

Juan Pablo Tettamanti, A. Latini, M. Aguirre
{"title":"基于Matlab/Simulink的电力电子控制FPGA快速设计实例","authors":"Juan Pablo Tettamanti, A. Latini, M. Aguirre","doi":"10.1109/SPL.2011.5782627","DOIUrl":null,"url":null,"abstract":"This paper deals with the problem of the design of an all-digital implementation of a three-phase PLL and the control logic of a shunt active filter implemented with a Multilevel Current Source Inverter (MCSI). The active filter is connected to the medium voltage level of a power distribution system where compensation of reactive power and harmonics is mandatory. The PLL is essential to obtain a reference frame for grid synchronization. The performance of proposed PLL structure and logic control is simulated via Matlab/Simulink. The proposed PLL structure shows fast synchronization and adequate tolerance to grid voltage unbalance. Both the PLL and the control logic can be downloaded and tested on a Field-Programmable-Gate-Array (FPGA) using the same software tool.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An example of rapid design of power electronics control with FPGA in Matlab/Simulink\",\"authors\":\"Juan Pablo Tettamanti, A. Latini, M. Aguirre\",\"doi\":\"10.1109/SPL.2011.5782627\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper deals with the problem of the design of an all-digital implementation of a three-phase PLL and the control logic of a shunt active filter implemented with a Multilevel Current Source Inverter (MCSI). The active filter is connected to the medium voltage level of a power distribution system where compensation of reactive power and harmonics is mandatory. The PLL is essential to obtain a reference frame for grid synchronization. The performance of proposed PLL structure and logic control is simulated via Matlab/Simulink. The proposed PLL structure shows fast synchronization and adequate tolerance to grid voltage unbalance. Both the PLL and the control logic can be downloaded and tested on a Field-Programmable-Gate-Array (FPGA) using the same software tool.\",\"PeriodicalId\":6329,\"journal\":{\"name\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2011.5782627\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782627","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

本文研究了三相锁相环的全数字实现和用多电平电流源逆变器(MCSI)实现的并联有源滤波器的控制逻辑设计问题。有源滤波器连接到配电系统的中压级,其中无功功率和谐波补偿是强制性的。锁相环是获得电网同步参考系的关键。通过Matlab/Simulink对所提出的锁相环结构和逻辑控制的性能进行了仿真。所提出的锁相环结构同步速度快,对电网电压不平衡有足够的容忍度。锁相环和控制逻辑都可以下载并使用相同的软件工具在现场可编程门阵列(FPGA)上进行测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
An example of rapid design of power electronics control with FPGA in Matlab/Simulink
This paper deals with the problem of the design of an all-digital implementation of a three-phase PLL and the control logic of a shunt active filter implemented with a Multilevel Current Source Inverter (MCSI). The active filter is connected to the medium voltage level of a power distribution system where compensation of reactive power and harmonics is mandatory. The PLL is essential to obtain a reference frame for grid synchronization. The performance of proposed PLL structure and logic control is simulated via Matlab/Simulink. The proposed PLL structure shows fast synchronization and adequate tolerance to grid voltage unbalance. Both the PLL and the control logic can be downloaded and tested on a Field-Programmable-Gate-Array (FPGA) using the same software tool.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Using partial reconfigurability to aid debugging of FPGA designs Architecture driven memory allocation for FPGA based real-time video processing systems Soft error in FPGA-implemented asynchronous circuits Experiences applying framework-based functional verification to a design for programmable logic A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1