20纳米以下CMOS FinFET技术

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Pub Date : 2001-12-02 DOI:10.1109/IEDM.2001.979526

Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, T. King, J. Bokor, C. Hu

{"title":"20纳米以下CMOS FinFET技术","authors":"Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, T. King, J. Bokor, C. Hu","doi":"10.1109/IEDM.2001.979526","DOIUrl":null,"url":null,"abstract":"A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"26 1","pages":"19.1.1-19.1.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"213","resultStr":"{\"title\":\"Sub-20 nm CMOS FinFET technologies\",\"authors\":\"Yang-Kyu Choi, N. Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, E. Anderson, T. King, J. Bokor, C. Hu\",\"doi\":\"10.1109/IEDM.2001.979526\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"26 1\",\"pages\":\"19.1.1-19.1.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"213\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979526\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979526","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 213

摘要

报道了一种sub- 20nm CMOS双栅finfet的简化制造工艺。与之前的FinFET相比，它是一个更易于制造的过程，并且具有更少的重叠电容(1999,2000)。提出了电子束光刻和间隔光刻两种不同的制版方法。利用LPCVD技术制备的选择性锗可减小寄生串联电阻，提高驱动电流。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Sub-20 nm CMOS FinFET technologies

A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)

自引率

0.00%

发文量