使CMOS向3nm及以上扩展

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI:10.1109/VLSIT.2018.8510683

A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J. Ryckaert

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引用次数: 17

摘要

我们看几个必要的缩放助推器，以实现CMOS面积缩放到2nm节点。我们考虑了标准单元面积缩放、晶体管结构、SRAM和BEOL等方面。我们还演示了这种缩放助推器的集成流程和硬件可行性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Enabling CMOS Scaling Towards 3nm and Beyond

We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.

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2018 IEEE Symposium on VLSI Technology

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