一种可重构的GF(2M)椭圆曲线密码协处理器

M. Morales-Sandoval, C. Feregrino-Uribe, R. Cumplido, I. Algredo-Badillo
{"title":"一种可重构的GF(2M)椭圆曲线密码协处理器","authors":"M. Morales-Sandoval, C. Feregrino-Uribe, R. Cumplido, I. Algredo-Badillo","doi":"10.1109/SPL.2011.5782650","DOIUrl":null,"url":null,"abstract":"Elliptic Curve Cryptography (ECC) is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. This makes ECC a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. Regardless there are several related works in the literature, to our knowledge this is the first ECC coprocessor that makes use of a partial reconfigurable methodology to deal with interoperability problems in ECC. A suitable application of the proposed reconfigurable coprocessor is the security protocol IPSec, where the domain parameters for ECC-based cryptographic schemes, like digital signature or encryption, have to be negotiated and agreed upon by the communication partners at run time.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A reconfigurable GF(2M) elliptic curve cryptographic coprocessor\",\"authors\":\"M. Morales-Sandoval, C. Feregrino-Uribe, R. Cumplido, I. Algredo-Badillo\",\"doi\":\"10.1109/SPL.2011.5782650\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Elliptic Curve Cryptography (ECC) is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. This makes ECC a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. Regardless there are several related works in the literature, to our knowledge this is the first ECC coprocessor that makes use of a partial reconfigurable methodology to deal with interoperability problems in ECC. A suitable application of the proposed reconfigurable coprocessor is the security protocol IPSec, where the domain parameters for ECC-based cryptographic schemes, like digital signature or encryption, have to be negotiated and agreed upon by the communication partners at run time.\",\"PeriodicalId\":6329,\"journal\":{\"name\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2011.5782650\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782650","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21

摘要

椭圆曲线密码学(ECC)是一种在不降低安全级别的前提下,使用比其他已知公钥加密算法更短的密钥提供安全信息服务的密码学。这使得ECC成为在受限设备(如移动设备)中实现安全服务的一个很好的选择。然而,国际标准推荐的ECC实现参数的多样性导致了ECC实现之间的互操作性问题。这项工作提出了一种用于ECC的新型FPGA协处理器的设计和实现结果,该协处理器可以在运行时重新配置以支持不同的实现参数,从而支持不同的安全级别。不管文献中有几个相关的作品,据我们所知,这是第一个ECC协处理器,它利用部分可重构的方法来处理ECC中的互操作性问题。提议的可重构协处理器的一个合适应用是安全协议IPSec,其中基于ecc的加密方案的域参数,如数字签名或加密,必须在运行时由通信伙伴协商和商定。
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A reconfigurable GF(2M) elliptic curve cryptographic coprocessor
Elliptic Curve Cryptography (ECC) is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. This makes ECC a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. Regardless there are several related works in the literature, to our knowledge this is the first ECC coprocessor that makes use of a partial reconfigurable methodology to deal with interoperability problems in ECC. A suitable application of the proposed reconfigurable coprocessor is the security protocol IPSec, where the domain parameters for ECC-based cryptographic schemes, like digital signature or encryption, have to be negotiated and agreed upon by the communication partners at run time.
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