在可重构硬件和gpu中的快速并行音频指纹识别实现

J. Martínez, Jaime Vitola, Adriana Sanabria, C. Pedraza
{"title":"在可重构硬件和gpu中的快速并行音频指纹识别实现","authors":"J. Martínez, Jaime Vitola, Adriana Sanabria, C. Pedraza","doi":"10.1109/SPL.2011.5782656","DOIUrl":null,"url":null,"abstract":"One of the main challenges that Music Information Retrieval (MIR) faces is performance. This paper presents an algorithm based on fingerprinting techniques implemented in a low-cost embedded reconfigurable platform. This fast algorithm is even faster when implemented in parallel for a GPU platform. The hit rate of the implementations is practically 100% and the response time is two times faster than the response time of a top class PC, which means MIR times of up to 65 audio tracks in real time.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Fast parallel audio fingerprinting implementation in reconfigurable hardware and GPUs\",\"authors\":\"J. Martínez, Jaime Vitola, Adriana Sanabria, C. Pedraza\",\"doi\":\"10.1109/SPL.2011.5782656\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"One of the main challenges that Music Information Retrieval (MIR) faces is performance. This paper presents an algorithm based on fingerprinting techniques implemented in a low-cost embedded reconfigurable platform. This fast algorithm is even faster when implemented in parallel for a GPU platform. The hit rate of the implementations is practically 100% and the response time is two times faster than the response time of a top class PC, which means MIR times of up to 65 audio tracks in real time.\",\"PeriodicalId\":6329,\"journal\":{\"name\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2011.5782656\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782656","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

音乐信息检索(MIR)面临的主要挑战之一是性能问题。提出了一种在低成本嵌入式可重构平台上实现的基于指纹识别技术的算法。这种快速算法在GPU平台上并行实现时甚至更快。实现的命中率几乎是100%,响应时间比顶级PC的响应时间快两倍,这意味着实时多达65个音轨的MIR时间。
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Fast parallel audio fingerprinting implementation in reconfigurable hardware and GPUs
One of the main challenges that Music Information Retrieval (MIR) faces is performance. This paper presents an algorithm based on fingerprinting techniques implemented in a low-cost embedded reconfigurable platform. This fast algorithm is even faster when implemented in parallel for a GPU platform. The hit rate of the implementations is practically 100% and the response time is two times faster than the response time of a top class PC, which means MIR times of up to 65 audio tracks in real time.
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