H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon
{"title":"高度可制造的低功耗和高性能11LPP平台技术，用于移动和GPU应用","authors":"H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon","doi":"10.1109/VLSIT.2018.8510694","DOIUrl":null,"url":null,"abstract":"11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"213-214"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications\",\"authors\":\"H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon\",\"doi\":\"10.1109/VLSIT.2018.8510694\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"13 1\",\"pages\":\"213-214\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510694\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510694","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications
11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.
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