Y.H. Kim, C. Lee, T. Jeon, W. Bai, C. Choi, S.J. Lee, L. Xinjian, R. Clarks, D. Roberts, D. Kwong
{"title":"用于亚100nm MOS器件的高品质CVD TaN栅电极","authors":"Y.H. Kim, C. Lee, T. Jeon, W. Bai, C. Choi, S.J. Lee, L. Xinjian, R. Clarks, D. Roberts, D. Kwong","doi":"10.1109/IEDM.2001.979596","DOIUrl":null,"url":null,"abstract":"In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"106 1","pages":"30.5.1-30.5.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"High quality CVD TaN gate electrode for sub-100 nm MOS devices\",\"authors\":\"Y.H. Kim, C. Lee, T. Jeon, W. Bai, C. Choi, S.J. Lee, L. Xinjian, R. Clarks, D. Roberts, D. Kwong\",\"doi\":\"10.1109/IEDM.2001.979596\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"106 1\",\"pages\":\"30.5.1-30.5.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979596\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979596","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High quality CVD TaN gate electrode for sub-100 nm MOS devices
In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.