采用片末组装技术构建C4凸块的FO-MCM

Chih-Hsun Hsu, Wen-Yang Li, Chi‐Jen Chen, Y. Jiang, Jui-Feng Tai, Chang-Fu Lin, C. Chung
{"title":"采用片末组装技术构建C4凸块的FO-MCM","authors":"Chih-Hsun Hsu, Wen-Yang Li, Chi‐Jen Chen, Y. Jiang, Jui-Feng Tai, Chang-Fu Lin, C. Chung","doi":"10.1109/ECTC.2019.00009","DOIUrl":null,"url":null,"abstract":"Chip last assembly technology is complex and higher cost for fan-out wafer level package (FOWLP). But, this technology is fit well for very high density interconnection packages. This article presents chip last assembly technology using C4 bump-first for fan out multi-chip module (FO-MCM) package. The objective is to reduce cycle-time. A chip module with 28 x 30 mm was fabricated using 2 daisy-chain Si dies that bonded onto 2/2 µm line/space redistribution layers (RDLs). This module was then assembled on high density substrate with size of 70 x 70 mm. This FOMCM package is constructed using C4 first process. C4 bumps were built on same side of the carrier after RDL was fabricated. The assemblies were protected and bonded on the carrier using temporary bond glue. The 1st carrier was then de-bonded. High I/O Si dies were attached onto the opposite side of the carrier followed by molding. The difference between C4 first and C4 last is the Si dies that were attached and molded with the carrier first then fabricated the C4 bumps. C4 first process has the challenge is micro-pads pattern shift between Si dies. By increasing the RDL density, one could reduce the irregular of micro-pads pattern shift. Additionally, by reducing the thermal budget and using higher Tg of the temporary bond glue, the pattern shift was improved to less than 5 mm. Additionally, the wafer warpage of C4 first was found consistently warped at the same side, thus the process was easier to control as compared to C4 last. The assembled FOMCM packages were then stressed for reliability tests. It passed 1000 hours of high temperature storage life test; MSL4 preconditioning with 1000 thermal cycles under B-conditions (-55~125 °C) and 192 hours unbiased high accelerated stress. Details of the results will be presented and discussed.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"7-13"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology\",\"authors\":\"Chih-Hsun Hsu, Wen-Yang Li, Chi‐Jen Chen, Y. Jiang, Jui-Feng Tai, Chang-Fu Lin, C. Chung\",\"doi\":\"10.1109/ECTC.2019.00009\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip last assembly technology is complex and higher cost for fan-out wafer level package (FOWLP). But, this technology is fit well for very high density interconnection packages. This article presents chip last assembly technology using C4 bump-first for fan out multi-chip module (FO-MCM) package. The objective is to reduce cycle-time. A chip module with 28 x 30 mm was fabricated using 2 daisy-chain Si dies that bonded onto 2/2 µm line/space redistribution layers (RDLs). This module was then assembled on high density substrate with size of 70 x 70 mm. This FOMCM package is constructed using C4 first process. C4 bumps were built on same side of the carrier after RDL was fabricated. The assemblies were protected and bonded on the carrier using temporary bond glue. The 1st carrier was then de-bonded. High I/O Si dies were attached onto the opposite side of the carrier followed by molding. The difference between C4 first and C4 last is the Si dies that were attached and molded with the carrier first then fabricated the C4 bumps. C4 first process has the challenge is micro-pads pattern shift between Si dies. By increasing the RDL density, one could reduce the irregular of micro-pads pattern shift. Additionally, by reducing the thermal budget and using higher Tg of the temporary bond glue, the pattern shift was improved to less than 5 mm. Additionally, the wafer warpage of C4 first was found consistently warped at the same side, thus the process was easier to control as compared to C4 last. The assembled FOMCM packages were then stressed for reliability tests. It passed 1000 hours of high temperature storage life test; MSL4 preconditioning with 1000 thermal cycles under B-conditions (-55~125 °C) and 192 hours unbiased high accelerated stress. Details of the results will be presented and discussed.\",\"PeriodicalId\":6726,\"journal\":{\"name\":\"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"30 1\",\"pages\":\"7-13\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2019.00009\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2019.00009","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

扇出式晶圆级封装(FOWLP)的芯片末装工艺复杂且成本较高。但是,该技术适合于非常高密度的互连封装。本文介绍了采用C4碰撞优先的扇出多芯片模块(FO-MCM)封装芯片末装技术。目标是减少循环时间。一个28 x 30 mm的芯片模块是用2个菊花链硅模制成的,硅模粘接在2/2µm的线/空间再分配层(rdl)上。然后将该模块组装在尺寸为70 x 70 mm的高密度基板上。这个FOMCM包是使用C4第一个过程构造的。在RDL制造后,在航母的同一侧建造C4凸起。这些组件被保护并使用临时粘合胶粘合在载体上。然后,第一艘航母被解除了束缚。高I/O Si模具附着在载体的对面,然后成型。C4第一和C4最后之间的区别是Si模具附着和模塑与载体,然后制造C4颠簸。C4第一工艺所面临的挑战是微晶片在硅模之间的模式移位。通过增加RDL密度,可以减少微片模式移动的不规则性。此外,通过减少热收支和使用更高Tg的临时粘合胶,图案位移改善到小于5毫米。此外,发现C4的晶圆翘曲始终在同一侧弯曲,因此与C4相比,该过程更容易控制。然后对组装好的FOMCM包进行了可靠性测试。通过1000小时高温贮存寿命试验;MSL4预处理在b条件下(-55~125°C)进行1000个热循环和192小时无偏高加速应力。结果的细节将被展示和讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology
Chip last assembly technology is complex and higher cost for fan-out wafer level package (FOWLP). But, this technology is fit well for very high density interconnection packages. This article presents chip last assembly technology using C4 bump-first for fan out multi-chip module (FO-MCM) package. The objective is to reduce cycle-time. A chip module with 28 x 30 mm was fabricated using 2 daisy-chain Si dies that bonded onto 2/2 µm line/space redistribution layers (RDLs). This module was then assembled on high density substrate with size of 70 x 70 mm. This FOMCM package is constructed using C4 first process. C4 bumps were built on same side of the carrier after RDL was fabricated. The assemblies were protected and bonded on the carrier using temporary bond glue. The 1st carrier was then de-bonded. High I/O Si dies were attached onto the opposite side of the carrier followed by molding. The difference between C4 first and C4 last is the Si dies that were attached and molded with the carrier first then fabricated the C4 bumps. C4 first process has the challenge is micro-pads pattern shift between Si dies. By increasing the RDL density, one could reduce the irregular of micro-pads pattern shift. Additionally, by reducing the thermal budget and using higher Tg of the temporary bond glue, the pattern shift was improved to less than 5 mm. Additionally, the wafer warpage of C4 first was found consistently warped at the same side, thus the process was easier to control as compared to C4 last. The assembled FOMCM packages were then stressed for reliability tests. It passed 1000 hours of high temperature storage life test; MSL4 preconditioning with 1000 thermal cycles under B-conditions (-55~125 °C) and 192 hours unbiased high accelerated stress. Details of the results will be presented and discussed.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Further Enhancement of Thermal Conductivity through Optimal Uses of h-BN Fillers in Polymer-Based Thermal Interface Material for Power Electronics A Novel Design of a Bandwidth Enhanced Dual-Band Impedance Matching Network with Coupled Line Wave Slowing A New Development of Direct Bonding to Aluminum and Nickel Surfaces by Silver Sintering in air Atmosphere Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing Applications Multilayer Glass Substrate with High Density Via Structure for All Inorganic Multi-chip Module
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1